In the field of non-volatile memories, flash memory scaling beyond a 45 nm node has become a real issue. Technologies to face this challenge are ferroelectric, magnetic and phase change memories, the latter one being promising for the replacement of flash and showing characteristic that may allow replacement of other types of memories such as DRAM. Phase change memories are a possible solution for the unified memory being an important step in the electronics art. OTP (“on time programmable”) and MTP (“multiple times programmable”) memories open a field that may present a great opportunity for phase change memories as well.
Phase change memories are based on a reversible memory switching using, for instance, chalcogenide materials. The ability of these materials to undergo fast phase transition has led to the development of rewritable optical media (CD, DVD). The chalcogenide phase change materials may be divided in two classes which are slightly different compositions, based on their crystallization mechanism. The “nucleation dominated” material GeTe—Sb2Te3 tie line such as Ge2Sb2Te5 are generally used in ovonic unified memory (OUM) devices. In this concept, the phase change material may be in contact with a bottom-resistive electrode to switch reversibly to a small volume of phase change material. “Fast growth material”, known in optical storage application (CD-RW/DVD+RW), enable very fast switching (for instance 10 ns) with a proper phase stability. In such an approach, the active part of a memory device may be a phase change line formed in between two electrodes formed in the back end of line processing (BEOL) of a CMOS-based front end of line (FEOL).
Thus, phase change materials may be used to store information. The operational principle of these materials is a change of phase. In a crystalline phase, the material structure is, and thus properties are, different from the properties in the amorphous phase.
The programming of a phase change material is based on the difference between the resistivity of the material in its amorphous and crystalline phase. To switch between both phases, an increase of the temperature is required. Very high temperatures with rapid cooling down will result in an amorphous phase, whereas a smaller increase in temperature or slower cooling down leads to a crystalline phase. Sensing the different resistances may be done with a small current that does not cause substantial heating.
The increase in temperature may be obtained by applying a pulse to the memory cell. A high current density caused by the pulse may lead to a local temperature increase. Depending on the duration and amplitude of the pulse, the resulting phase will be different. Larger pulse amplitudes, so-called RESET pulses, may amorphize the cells, whereas smaller pulse amplitudes will SET the cell to its crystalline state, these pulses are also called SET pulses.
WO 2006/079952 A1 discloses a phase change resistor device, which has a phase change material (PCM) for which the phase transition occurs inside the PCM and not at the interface with a contact electrode. The PCM is an elongate line structure surrounded by the conductive electrode portions at its lateral sides, and is formed in a CMOS backend process. There is a line of PCM, which has a constant diameter or cross section, formed with reduced dimensions by using a spacer as a hard mask. A “one dimensional” layer of the PCM electrically connects the first contact electrode and the second contact electrode. The contact resistance between the one-dimensional layer of PCM and the first contact electrode at the second contact electrode is lower than the resistance of a central or intervening portion of the line.
However, programming conventional memory cells may require high power consumption.